1. Field of the Invention
The present invention relates to a column switch in a memory device having a logic calculation function used at reading tag memory data of a cache memory and a cache memory using the same.
2. Description of the Related Art
In a computer and other data processing apparatus including a central processing unit (CPU) and a main memory, a cache memory is provided separately from the main memory and able to be accessed at a high speed. When the main memory in the CPU is accessed, accessed data and tag data relating to an address information of the data are temporarily stored in the cache memory. When the CPU again accesses data stored at the same address in the main memory next time, the data stored in the cache memory is output to the CPU instead of that stored in the main memory. Therefore, by using the cache memory, data accessing at a high speed can be realized when repeatedly accessing to data in the same memory area in the main memory, and currently, most computers are provided with cache memories. Also, an IC chip wherein a CPU and cache memory are integrated on the same semiconductor chip has become a product.
FIG. 1 is a view of an example of the configuration of a data processing apparatus including a cache memory. As shown in the figure, the data processing apparatus is comprised of a CPU 10, a main memory 20 and a cache memory 30. A memory access, for example, reading data from the main memory is performed via a data but 40 and an address bus 50. The CPU 10 outputs an address signal ADR to the main memory 20 via the address bus 50, data stored at an address specified by the address signal ADR is read and transferred to the CPU 10 via the data bus.
At the same time with the above reading, the read data and a part of the address signal ADR relating thereto (for example, upper n bits in the m-bit address signal ADR, hereinafter, it is referred to as ADRa. Here, m and n are natural numbers and m greater than n.) are written in the cache memory 30. When the CPU reads data at the same address as the previous time from the main memory 20, data stored in the cache memory is read instead of that in the main memory 20 and supplied to the CPU 10. Since the cache memory 30 is comprised for example of an SRAM able to be accessed at a high speed, data reading at a higher speed can be realized compared with the main memory.
FIG. 2 is a view of an example of the configuration of the cache memory 30. As shown in the figure, the cache memory 30 is comprised of a cache control circuit 31, a tag memory 32, a data memory 33, a tag data reading circuit 34 and a hit signal generation circuit 35. Note that FIG. 2 is a simplified view showing only a portion relating to data reading in the cache memory 30. In an actual cache memory, partial circuits, such as a writing circuit for storing data, a data reading circuit for reading data from the data memory 33 at the time of hitting, etc., are included in the tag memory 32 and data memory 33, respectively, but they will be omitted here.
The cache control circuit 31 respectively controls writing and reading of data in the tag memory 32 and data memory 33. The tag memory 31 stores address information relating to data stored in the data memory 33 (hereinafter, referred to as tag data). Namely, when reading data from the main memory 20, reading data is stored in the data memory 33 and tag data relating to the reading data is stored in the tag memory 32.
The tag data reading circuit 34 reads the tag data TGD stored in the tag memory 32 and outputs to the hit signal generation circuit 35.
The hit signal generation circuit 35 compares the tag data TGD read by the tag reading circuit 34 and the address ADRa from the CPU 10 and outputs a hit signal Shit when the tag data TGD matches the address ADRa.
The cache control circuit 31, when receiving the hit signal Shit from the hit signal generation circuit 35, outputs a control signal SC to a not shown data reading circuit, reads data from the data memory 32 by the data reading circuit and outputs the same to the data bus 40.
With the provision of above mentioned cache memory 30, a high speed accessing can be realized and performance of the data processing apparatus can be improved without using any costly high speed memory as a main memory.
In the above cache memory of the related art, however, the tag data reading circuit 34 reads tag data from the tag memory 32 and a comparison circuit compares so as to generate a bit signal Shit. The comparison circuit is comprised, for example, of an exclusive OR (XOR) circuit. A logic circuit performing XOR calculation is normally not capable of directly processing a weak read signal output from the tag memory, thus, the tag data reading circuit 34 amplifies the read signal by a sense amplifier to convert to have a sufficient amplitude level so that the logic circuit can perform processing and input the same to the logic circuit. The logic circuit for performing XOR calculation is comprised, for example, of a CMOS circuit and calculates a signal of a CMOS level, therefore, there arises a disadvantage that the processing speed declines due to dealing with a signal having a large amplitude and a generation speed of the hit signal declines.
FIG. 3 is a view of a partial circuit of the cache memory including a cache control circuit 31, tag memory 32, tag data reading circuit 34 and a hit signal generation circuit 35. As shown in the figure, the tag data reading circuit 34 is comprised of a row decoder 301, column decoder 302, a column switch 303, sense amplifier 304, a level conversion circuit 305 and an exclusive OR circuit 306.
The tag memory 32 is a memory cell array comprised, for example, of a plurality of memory cells arranged in a matrix. Memory cells of the respective rows are connected to a plurality of word lines and memory cells of the respective columns are connected to a plurality of bit lines. The word lines and bit lines are selected by the row decoder 301 and the column decoder 302. Note that the row decoder 301 and the column decoder 302 are controlled by the cache control circuit 31.
The reading from the tag memory 32 is performed on a memory cell connected to a bit line selected by the column decoder 302 among the memory cells connected to the word lines selected by the row decoder 301. The column decoder 302 controls the column switch 303 and a read signal on the selected bit line is transferred to the sense amplifier 304. Stored data in the selected memory cell in the tag memory 32 is read in accordance with a voltage level of a read signal of the selected bit line by the sense amplifier 304. The level conversion circuit 305 converts a level of an output signal of the sense amplifier 304 and provides the same to the exclusive OR circuit 36. For example, assuming that the XOR circuit 306 is comprised by the CMOS circuit, the level conversion circuit 305 converts an amplitude level of the output signal of the sense amplifier 304 to be a CMOS level.
The XOR circuit 306 obtains an exclusive OR of every bit in the tag data from the level conversion circuit 305 and in the address signal ADRa input via the address bus, and outputs the results to the hit signal generation circuit 35. The XOR circuit 306 compares the read tag data and an input address signal ADRa and provides the comparison result to the hit signal generation circuit 35. The hit signal generation circuit 35 generates a hit signal Shit in accordance with matching or unmatching of the comparison result and supplies the same to the cache control circuit 31.
As explained above, in the XOR circuit 306 used for comparison calculation of the tag data and the address signal ADRa, for example a signal of a CMOS level is dealt, so a weak signal output from the column switch 303 is amplified in the sense amplifier 304, converted by the level conversion circuit 305, and then, supplied to the XOR circuit 306. Since logic calculation is performed on a signal having a large amplitude, the calculation time of the comparison result becomes long and a cache at a high speed is affected.
An object of the present invention is to provide a cache memory capable of making an access time short by realizing high speed logic calculation of an address and tag information by using a column switch having a logic calculation function.
To attain the above object according to the present invention, there is provided a column switch in a memory device, wherein each memory cell in the memory device is connected to a bit line and an auxiliary bit line, for outputting a differential voltage set on the bit line and auxiliary bit line in accordance with memory data of the memory cell at when reading data from the memory cell,
said column switch receiving an input signal of a first or second logic state, and outputting a differential signal on the bit line and auxiliary bit line to the sense amplifier when the input signal is in the first logic state, and outputting a differential signal on the bit line and auxiliary bit line being logically inversed and outputs to the sense amplifier when the input signal is in the second logic state.
Preferably, a column switch of the present invention comprises a first switching element connected between the bit line and a first input terminal of the sense amplifier; a second switching element connected between the auxiliary bit line and a second input terminal of the sense amplifier; a third switching element connected between the bit line and the second input terminal of the sense amplifier; and a fourth switching element connected between the auxiliary bit line and the first input terminal of the sense amplifier; and wherein the first and second switching elements become conductive when the input signal is in the first logic state, and the third and fourth switching elements become conductive when the input signal is in the second logic state.
Preferably, the first and second switching elements are respectively connected between the bit line and the first input terminal of the sense amplifier, and between the auxiliary bit line and the second input terminal of the sense amplifier, and comprised of a transistor whose control terminal is applied the input signal; and the third and fourth switching elements are respectively connected between the auxiliary bit line and the first input terminal of the sense amplifier, and between the bit line and the second input terminal of the sense amplifier, and comprised of a transistor whose control terminal is applied a logically inversed signal of the input signal.
Furthermore, according to the present invention, there is provided a cache memory comprising a tag memory for storing tag information and a data memory for storing data corresponding to the tag information, for comparing an address and the tag information stored in the tag memory at the time of reading, and outputting the data corresponding to the tag information when the address and the tag information are matched, comprises a column switch being set a signal potential of a bit line connected to the respective memory cells in accordance with memory data of respective cells in the tag memory, and outputting a signal potential or a logically inversed signal of the signal potential of the bit line in accordance with the respective bits of the address being xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d; a sense amplifier for amplifying an output signal of the column switch; and a hit judgement circuit for judging whether or not the address and the tag information are matched in accordance with an output signal of the sense amplifier.
According to the present invention, a column switch having a logic calculation function is provided to a memory cell array of the tag memory for storing tag information, and the column switch controls a differential signal read from the memory cell of the tag memory to the bit line and auxiliary bit line in accordance with the respective bits of the address signal and outputs to the sense amplifier. For example, when a predetermined bit of the address signal is xe2x80x9c0xe2x80x9d, a differential signal on the bit line and auxiliary bit line is output as it is to the sense amplifier, while when a predetermined bit of the address signal is xe2x80x9c1xe2x80x9d, a logically inversed signal of a differential signal on the bit line and auxiliary bit line is output to the sense amplifier, thus, XOR calculation is performed on every bit of the read tag data and the address.
The signal from the column switch is amplified by the sense amplifier, and it is judged whether the tag information and the address are matched in accordance therewith, and a hit signal is output when they are matched. Since the XOR calculation is performed on the read signal having a small amplitude on the bit line as it is, a high speed logic calculation can be realized and a cache memory of high performance capable of attaining a shorter accessing time can be realized.